Slope

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It is easy to use, requiring few external components. A single supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corresponding to a power consumption of under 50 mW at 3 V, plus the limiter bias current, determined by the application and typically 2 mA, providing a limiter gain of 90 dB when using 200 Ω loads. A CMOS-compatible control interface can enable the AD8306 within about 500 ns and disable it to a standby current of under 1 µA.
The six cascaded amplifier/limiter cells in the main path have a small signal gain of 12.04 dB (×4), with a -3 dB bandwidth of 850 MHz, providing a total gain of 72 dB. The programmable output stage provides a further 18 dB of gain. The input is fully differential and presents a moderately high impedance (1 kΩ in parallel with 2.5 pF). The input-referred noise-spectral-density, when driven from a terminated 50 Ω, source is 1.28 nV/√Hz, equivalent to a noise figure of 3 dB. The sensitivity of the AD8306 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An additional four detectors, driven by a broadband attenuator, are used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from -91 dBV (-78 dBm at the 50 Ω level) to a maximum permissible value of +9 dBV, using a balanced drive of antiphase inputs each of 2 V in amplitude, which would correspond to a sine wave power of +22 dBm if the differential input were terminated in 50 Ω. Through laser trimming, the slope of the RSSI output is closely controlled to 20 mV/dB, while the intercept is set to -108 dBV (-95 dBm re 50 Ω). These scaling parameters are determined by a band-gap voltage reference and are substantially independent of temperature and supply. The logarithmic law conformance is typically within ± 0.4 dB over the central 80 dB of this range at any frequency between 10 MHz and 200 MHz, and is degraded only slightly at 400 MHz.
The RSSI response time is nominally 73 ns (10%-90%). The averaging time may be increased without limit by the addition of an external capacitor. The full output of 2.34 V at the maximum input of +9 dBV can drive any resistive load down to 50 Ω and this interface remains stable with any value of capacitance on the output. The AD8306 is fabricated on an advanced complementary bipolar process using silicon-on-insulator isolation techniques and is available in the industrial temperature range of -40°C to +85°C, in a 16-lead narrow body SO package. The AD8306 is also available for the full military temperature range of -55°C to +125°C, in a 16-lead side-brazed ceramic DIP. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

PRODUCT OVERVIEW
The AD8306 is built on an advanced dielectrically-isolated complementary bipolar process using thin-film resistor technology for accurate scaling. It follows well-developed foundations proven over a period of some fifteen years, with constant refinement. The backbone of the AD8306 ( Figure 19) comprises a chain of six main amplifier/limiter stages, each having a gain of 12.04 dB (×4) and small-signal -3 dB bandwidth of 850 MHz.
The input interface at INHI and INLO (Pins 4 and 5) is fully differential. Thus it may be driven from either single-sided or balanced inputs, the latter being required at the very top end of the dynamic range, where the total differential drive may be as large as 4 V in amplitude.
The first six stages, also used in developing the logarithmic RSSI output, are followed by a versatile programmable-output, and thus programmable-gain, final limiter section. Its opencollector outputs are also fully differential, at LMHI and LMLO (Pins 12 and 13). This output stage provides a gain of 18 dB when using equal valued load and bias setting resistors and the pin-to-pin output is used. The overall voltage gain is thus 90 dB. When using R LIM = R LOAD = 200 Ω, the additional current consumption in the limiter is approximately 2.8 mA, of which 2 mA goes to the load. The ratio depends on R LIM (for example, when 20 Ω, the efficiency is 90%), and the voltage at the pin LMDR is rather more than 400 mV, but the total load current is accurately (400 mV)/R LIM .
The rise and fall times of the hard-limited (essentially squarewave) voltage at the outputs are typically 0.6 ns, when driven by a sine wave input having an amplitude of 316 µV or greater, and R LOAD = 50 Ω. The change in time-delay ("phase skew") over the input range -73 dBV (316 µV in amplitude, or -60 dBm in 50 Ω) to -3 dBV (1 V or +10 dBm) is ±56 ps (±2° at 100 MHz). The six main cells and their associated full-wave detectors, having a transconductance (g m ) form, handle the lower part of the dynamic range. Biasing for these cells is provided by two references, one of which determines their gain, the other being a band-gap cell which determines the logarithmic slope, and stabilizes it against supply and temperature variations. A special dc-offset-sensing cell (not shown in Figure 19) is placed at the end of this main section, and used to null any residual offset at the input, ensuring accurate response down to the noise floor. The first amplifier stage provides a short-circuited voltage-noise spectral-density of 1.07 nV/√Hz.
The last detector stage includes a modification to temperaturestabilize the log-intercept, which is accurately positioned so as to make optimal use of the full output voltage range. Four further "top end" detectors are placed at 12.04 dB taps along a passive attenuator, to handle the upper part of the range. The differential current-mode outputs of all ten detectors stages are summed with equal weightings and converted to a single-sided voltage by the output stage, generating the logarithmic (or RSSI) output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is, 400 mV per decade). The junction between the lower and upper regions is seamless, and the logarithmic law-conformance is typically well within ±0.4 dB over the 80 dB range from -80 dBV to 0 dBV (-67 dBm to +13 dBm).
The full-scale rise time of the RSSI output stage, which operates as a two-pole low-pass filter with a corner frequency of 3.5 MHz, is about 200 ns. A capacitor connected between FLTR (Pin 10) and VLOG can be used to lower the corner frequency (see below). The output has a minimum level of about 0.34 V (corresponding to a noise power of -78 dBm, or 17 dB above the nominal intercept of -95 dBm). This rather high baseline level ensures that the pulse response remains unimpaired at very low inputs.
The maximum RSSI output depends on the supply voltage and the load. An output of 2.34 V, that is, 20 mV/dB × (9 + 108) dB, is guaranteed when using a supply voltage of 4.5 V or greater and a load resistance of 50 Ω or higher, for a differential input of 9 dBV (a 4 V sine amplitude, using balanced drives). When using a 3 V supply, the maximum differential input may still be as high as -3 dBV (1 V sine amplitude), and the corresponding RSSI output of 2.1 V, that is, 20 mV/dB × (-3 + 108) dB is also guaranteed.
A fully-programmable output interface is provided for the hardlimited signal, permitting the user to establish the optimal output current from its differential current-mode output. Its magnitude is determined by the resistor R LIM placed between LMDR (Pin 9) and ground, across which a nominal bias voltage of ~400 mV appears. Using R LIM = 200 Ω, this dc bias current, which is commutated alternately to the output pins, LMHI and LMLO, by the signal, is 2 mA. (The total supply current is somewhat higher).
These currents may readily be converted to voltage form by the inclusion of load resistors, which will typically range from a few tens of ohms at 400 MHz to as high as 2 kΩ in lower frequency applications. Alternatively, a resonant load may be used to extract the fundamental signal and modulation sidebands, minimizing the out-of-band noise. A transformer or impedance matching network may also be used at this output. The peak voltage swing down from the supply voltage may be 1.2 V, before the output transistors go into saturation. (The Applications section provides further information on the use of this interface).
The supply current for all sections except the limiter output stage, and with no load attached to the RSSI output, is nominally 16 mA at T A = 27°C, substantially independent of supply voltage. It varies in direct proportion to the absolute temperature (PTAT). The RSSI load current is simply the voltage at VLOG divided by the load resistance (e.g., 2.4 mA max in a 1 kΩ load). The limiter supply current is 1.1 times that flowing in R LIM . The AD8306 may be enabled/disabled by a CMOScompatible level at ENBL (Pin 8).
In the following simplified interface diagrams, the components denoted with an uppercase "R" are thin-film resistors having a very low temperature-coefficient of resistance and high linearity under large-signal conditions. Their absolute value is typically within ± 20%. Capacitors denoted using an uppercase "C" have a typical tolerance of ± 15% and essentially zero temperature or

AD8306
-8-voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or ESD protection; these may be neither accurate nor stable. Component numbering in each of these interface diagrams is local.

Enable Interface
The chip-enable interface is shown in Figure 20. The current in R1 controls the turn-on and turn-off states of the band-gap reference and the bias generator, and is a maximum of 100 µA when Pin 8 is taken to 5 V. Left unconnected, or at any voltage below 1 V, the AD8306 will be disabled, when it consumes a sleep current of much less than 1 µA (leakage currents only); when tied to the supply, or any voltage above 2 V, it will be fully enabled.
The internal bias circuitry requires approximately 300 ns for either OFF or ON, while a delay of some 6 µs is required for the supply current to fall below 10 µA.  Figure 21 shows the essentials of the signal input interface. The parasitic capacitances to ground are labeled C P ; the differential input capacitance, C D , mainly due to the diffusion capacitance of Q1 and Q2. In most applications both input pins are accoupled. The switch S closes when Enable is asserted. When disabled, the inputs float, bias current I E is shut off, and the coupling capacitors remain charged. If the log amp is disabled for long periods, small leakage currents will discharge these capacitors. If they are poorly matched, charging currents at power-up can generate a transient input voltage which may block the lower reaches of the dynamic range until it has become much less than the signal. In most applications, the input signal will be single-sided, and may be applied to either Pin 4 or 5, with the remaining pin accoupled to ground. Under these conditions, the largest input signal that can be handled is -3 dBV (sine amplitude of 1 V) when operating from a 3 V supply; a +3 dBV input may be handled using a supply of 4.5 V or greater. When using a fullybalanced drive, the +3 dBV level may be achieved for the supplies down to 2.7 V and +9 dBV using >4.5 V. For frequencies in the range 10 MHz to 200 MHz these high drive levels are easily achieved using a matching network. Using such a network, having an inductor at the input, the input transient is eliminated.

Limiter Output Interface
The simplified limiter output stage is shown in Figure 22. The bias for this stage is provided by a temperature-stable reference voltage of nominally 400 mV which is forced across the external resistor R LIM connected from Pin 9 (LMDR, or limiter drive) by a special op amp buffer stage. The biasing scheme also introduces a slight "lift" to this voltage to compensate for the finite current gain of the current source Q3 and the output transistors Q1 and Q2. A maximum current of 10 mA is permissible (R LIM = 40 Ω). In special applications, it may be desirable to modulate the bias current; an example of this is provided in the Applications section. Note that while the bias currents are temperature stable, the ac gain of this stage will vary with temperature, by -6 dB over a 120°C range.
A pair of supply and temperature stable complementary currents is generated at the differential output LMHI and LMLO (Pins 12 and 13), having a square wave form with rise and fall times of typically 0.6 ns, when load resistors of 50 Ω are used. The voltage at these output pins may swing to 1.2 V below the supply voltage applied to VPS2 (Pin 15).
Because of the very high gain bandwidth product of this amplifier considerable care must be exercised in using the limiter outputs. The minimum necessary bias current and voltage swings should be used. These outputs are best utilized in a fully-differential mode. A flux-coupled transformer, a balun, or an output matching network can be selected to transform these voltages to a single-sided form. Equal load resistors are recommended, even when only one output pin is used, and these should always be returned to the same well decoupled node on the PC board. When the AD8306 is used only to generate an RSSI output, the limiter should be completely disabled by omitting R LIM and strapping LMHI and LMLO to VPS2.

RSSI Output Interface
The outputs from the ten detectors are differential currents, having an average value that is dependent on the signal input level, plus a fluctuation at twice the input frequency. The currents are summed at the internal nodes LGP and LGN shown in Figure 23. A further current I T is added to LGP, to position

AD8306
-9-the intercept to -108 dBV, by raising the RSSI output voltage for zero input, and to provide temperature compensation, resulting in a stable intercept. For zero signal conditions, all the detector output currents are equal. For a finite input, of either polarity, their difference is converted by the output interface to a singlesided voltage nominally scaled 20 mV/dB (400 mV per decade), at the output VLOG (Pin 16). This scaling is controlled by a separate feedback stage, having a tightly controlled transconductance. A small uncertainty in the log slope and intercept remains (see Specifications); the intercept may be adjusted (see Applications).  Figure 23. Simplified RSSI Output Interface

VPS2
The RSSI output bandwidth, f LP , is nominally 3.5 MHz. This is controlled by the compensation capacitor C1, which may be increased by adding an external capacitor, C F , between FLTR (Pin 10) and VLOG (Pin 16). An external 33 pF will reduce f LP to 350 kHz, while 360 pF will set it to 35 kHz, in each case with an essentially one-pole response. In general, the relationships (for f LP in MHz) are: Using a load resistance of 50 Ω or greater, and at any temperature, the peak output voltage may be at least 2.4 V when using a supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is consistent with the maximum permissible input levels. The incremental output resistance is approximately 0.3 Ω at low frequencies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.
The output is unconditionally stable with load capacitance, but it should be noted that while the peak sourcing current is over 100 mA, and able to rapidly charge even large capacitances, the internally provided sinking current is only 1 mA. Thus, the fall time from the 2 V level will be as long as 2 µs for a 1 nF load. This may be reduced by adding a grounded load resistance.

USING THE AD8306
The AD8306 exhibits very high gain from 1 MHz to over 1 GHz, at which frequency the gain of the main path is still over 65 dB. Consequently, it is susceptible to all signals, within this very broad frequency range, that find their way to the input terminals. It is important to remember that these are quite indistinguishable from the "wanted" signal, and will have the effect of raising the apparent noise floor (that is, lowering the useful dynamic range). Therefore, while the signal of interest may be an IF of, say, 200 MHz, any of the following could easily be larger than this signal at the lower extremities of its dynamic range: a 60 Hz hum, picked up due to poor grounding techniques; spurious coupling from digital logic on the same PC board; a strong EMI source; etc.
Very careful shielding is essential to guard against such unwanted signals, and also to minimize the likelihood of instability due to HF feedback from the limiter outputs to the input. With this in mind, the minimum possible limiter gain should be used. Where only the logarithmic amplifier (RSSI) function is required, the limiter should be disabled by omitting R LIM and tying the outputs LMHI and LMLO directly to VPS2. A good ground plane should be used to provide a low impedance connection to the common pins, for the decoupling capacitor(s) used at VPS1 and VPS2, and at the output ground. Note that COM2 is a special ground pin serving just the RSSI output.
The four pins labeled PADL tie down directly to the metallic lead frame, and are thus connected to the back of the chip. The process on which the AD8306 is fabricated uses a bonded-wafer technique to provide a silicon-on-insulator isolation, and there is no junction or other dc path from the back side to the circuitry on the surface. These paddle pins must be connected directly to the ground plane using the shortest possible lead lengths to minimize inductance.
The voltages at the two supply pins should not be allowed to differ greatly; up to 500 mV is permissible. It is desirable to allow VPS1 to be slightly more negative than VPS2. When the primary supply is greater than 2.7 V, the decoupling resistors R1 and R2 (Figure 24) may be increased to improve the isolation and lower the dissipation in the IC. However, since VPS2 supports the RSSI load current, which may be large, the value of R2 should take this into account. Figure 24 shows the connections required for most applications. The AD8306 is enabled by connecting ENBL to VPS1. The device is put into the sleep mode by grounding this pin. The inputs are ac-coupled by C1 and C2, which normally should have the same value (C C ). The input is, in this case, terminated with a 52.3 Ω resistor that combines with the AD8306's input resistance of 1000 Ω to give a broadband input impedance of 50 Ω. Alternatively an input matching network can be used (see Input Matching section). The 0.01 µF coupling capacitors and the resulting 50 Ω input impedance give a high-pass corner frequency of around 600 kHz.

Basic Connections for Log (RSSI) Output
(1/(2 π RC)), where C = (C1)/2. In high frequency applications, this corner frequency should be placed as high as possible, to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a lowpass filter should be added at the input for the same reason.
If the limiter output is not required, Pin 9 (LMDR) should be left open and Pins 12 and 13 (LMHI, LMLO) should be tied to VPS2 as shown in Figure 24. Figure 25 shows the output versus the input level in dBV, for sine inputs at 10 MHz, 50 MHz and 100 MHz (add 13 to the dBV number to get dBm Re 50 Ω. Figure 26 shows the typical logarithmic linearity (log conformance) under the same conditions.

Transfer Function in Terms of Slope and Intercept
The transfer function of the AD8306 is characterized in terms of its Slope and Intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8306 the slope is calibrated to be 20 mV/dB.
The intercept is the point at which the extrapolated linear response would intersect the horizontal axis. For the AD8306 the intercept is calibrated to be -108 dBV (-95 dBm). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range using the equation: where V OUT is the demodulated and filtered RSSI output, V SLOPE is the logarithmic slope, expressed in V/dB, P IN is the input signal, expressed in decibels relative to some reference level (either dBm or dBV in this case) and P O is the logarithmic intercept, expressed in decibels relative to the same reference level.
For example, for an input level of -33 dBV (-20 dBm), the output voltage will be The most widely used convention in RF systems is to specify power in dBm, that is, decibels above 1 mW in 50 Ω. Specification of log amp input level in terms of power is strictly a concession to popular convention; they do not respond to power (tacitly "power absorbed at the input"), but to the input voltage. The use of dBV, defined as decibels with respect to a 1 V rms sine wave, is more precise, although this is still not unambiguous because waveform is also involved in the response of a log amp, which, for a complex input (such as a CDMA signal) will not follow the rms value exactly. Since most users specify RF signals in terms of power-more specifically, in dBm/50 Ω-we use both dBV and dBm in specifying the performance of the AD8306, showing equivalent dBm levels for the special case of a 50 Ω environment. Values in dBV are converted to dBm re 50 Ω by adding 13.

Output Response Time and C F
The RSSI output has a low-pass corner frequency of 3.5 MHz, which results in a 10% to 90% rise time of 73 ns. For low frequency applications, the corner frequency can be reduced by adding an external capacitor, C F , between FLTR (Pin 10) and VLOG (Pin 16) as shown in Figure 24. For example, an external 33 pF will reduce the corner frequency to 350 kHz, while 360 pF will set it to 35 kHz, in each case with an essentially one-pole response.
Using the Limiter Figure 27 shows the basic connections for operating the limiter and the log output concurrently. The limiter output is a pair of differential currents of magnitude, I OUT , from high impedance (open-collector) sources. These are converted to equal-amplitude voltages by supply-referenced load resistors, R LOAD . The limiter output current is set by R LIM , the resistor connected between Pin 9 (LMDR) and ground. The limiter output current is set according the equation: and has an absolute accuracy of ± 5%.
The supply referenced voltage on each of the limiter pins will thus be given by:

AD8306
-11- Depending on the application, the resulting voltage may be used in a fully balanced or unbalanced manner. It is good practice to retain both load resistors, even when only one output pin is used. These should always be returned to the same well decoupled node on the PC board (see layout of evaluation board). The unbalanced, or single-sided mode, is more inclined to result in instabilities caused by the very high gain of the signal path. The limiter current may be set as high as 10 mA (which requires R LIM to be 40 Ω) and can be optionally increased somewhat beyond this level. It is generally inadvisable, however, to use a high bias current, since the gain of this wide bandwidth signal path is proportional to the bias current, and the risk of instability is elevated as R LIM is reduced (recommended value is 400 Ω).
However, as the size of R LOAD is increased, the bandwidth of the limiter output decreases from 585 MHz for R LOAD = R LIM = 50 Ω to 50 MHz for R LOAD = R LIM = 400 Ω (bandwidth = 210 MHz for R LOAD = R LIM = 100 Ω and 100 MHz for R LOAD = R LIM = 200 Ω). As a result, the minimum necessary limiter output level should be chosen while maintaining the required limiter bandwidth. For R LIM = R LOAD = 50 Ω, the limiter output is specified for input levels between -78 dBV (-65 dBm) and +9 dBV (+22 dBm). The output of the limiter may be unstable for levels below -78 dBV (-65 dBm). However, keeping R LIM above 100 Ω will make instabilities on the output less likely for input levels below -78 dBV.
A transformer or a balun (e.g., MACOM part number ETC1-1-13) can be used to convert the differential limiter output voltages to a single-ended signal.

Input Matching
Where either a higher sensitivity or a better high frequency match is required, an input matching network is valuable. Using a flux-coupled transformer to achieve the impedance transformation also eliminates the need for coupling capacitors, lowers any dc offset voltages generated directly at the input, and usefully balances the drives to INHI and INLO, permitting full utilization of the unusually large input voltage capacity of the AD8306.
The choice of turns ratio will depend somewhat on the frequency. At frequencies below 30 MHz, the reactance of the input capacitance is much higher than the real part of the input impedance. In this frequency range, a turns ratio of 2:9 will lower the effective input impedance to 50 Ω while raising the input voltage by 13 dB. However, this does not lower the effect of the short circuit noise voltage by the same factor, since there will be a contribution from the input noise current. Thus, the total noise will be reduced by a smaller factor. The intercept at the primary input will be lowered to -121 dBV (-108 dBm).
Impedance matching and drive balancing using a flux-coupled transformer is useful whenever broadband coupling is required. However, this may not always be convenient. At high frequencies, it will often be preferable to use a narrow-band matching network, as shown in Figure 28, which has several advantages. First, the same voltage gain can be achieved, providing increased sensitivity, but now a measure of selectively is simultaneously introduced. Second, the component count is low: two capacitors and an inexpensive chip inductor are needed. Third, the network also serves as a balun. Analysis of this network shows that the amplitude of the voltages at INHI and INLO are quite similar when the impedance ratio is fairly high (i.e., 50 Ω to 1000 Ω).  Figure 29 shows the response for a center frequency of 100 MHz. The response is down by 50 dB at one-tenth the center frequency, falling by 40 dB per decade below this. The very high frequency attenuation is relatively small, however, since in the limiting case it is determined simply by the ratio of the AD8306's input capacitance to the coupling capacitors. Table I provides

General Matching Procedure
For other center frequencies and source impedances, the following method can be used to calculate the basic matching parameters.

Step 1: Tune Out C IN
At a center frequency f C , the shunt impedance of the input capacitance C IN can be made to disappear by resonating with a temporary inductor L IN , whose value is given by when C IN = 2.5 pF. For example, at f C = 100 MHz, L IN = 1 µH.

Step 2: Calculate C O and L O
Now having a purely resistive input impedance, we can calculate the nominal coupling elements C O and L O , using (8) For the AD8306, R IN is 1 kΩ. Thus, if a match to 50 Ω is needed, at f C = 100 MHz, C O must be 7.12 pF and L O must be 356 nH.

Step 3: Split C O Into Two Parts
Since we wish to provide the fully-balanced form of network shown in Figure 28, two capacitors C1 = C2 each of nominally twice C O , shown as C M in the figure, can be used. This requires a value of 14.24 pF in this example. Under these conditions, the voltage amplitudes at INHI and INLO will be similar. A somewhat better balance in the two drives may be achieved when C1 is made slightly larger than C2, which also allows a wider range of choices in selecting from standard values. For example, capacitors of C1 = 15 pF and C2 = 13 pF may be used (making C O = 6.96 pF).

Step 4: Calculate L M
The matching inductor required to provide both L IN and L O is just the parallel combination of these:

Altering the Logarithmic Slope
Simple schemes can be used to increase and decrease the logarithmic slope as shown in Figure 30. For the AD8306, only power, ground and logarithmic output connections are shown; refer to Figure 24 for complete circuitry. In Figure 30(a), the op amp's gain of +2 increases the slope to 40 mV/dB. In Figure  30(b), the AD8031 buffers a resistive divider to give a slope of

AD8306
-13-10 mV/dB The AD8031 rail-to-rail op amp, used in both examples, can swing from 50 mV to 4.95 mV on a single +5 V supply. If high output current is required (> 10 mA), the AD8051, which also has rail-to-rail capability but can deliver up to 45 mA of output current, can be used.

APPLICATIONS
The AD8306 is a versatile and easily applied log-limiting amplifier. Being complete, it can be used with very few external components, and most applications can be accommodated using the simple connections shown in the preceding section. A few examples of more specialized applications are provided here.

High Output Limiter Loading
The AD8306 can generate a fairly large output power at its differential limiter output interface. This may be coupled into a 50 Ω grounded load using the narrow-band coupling network following similar lines to those provided for input matching. Alternatively, a flux-linked transformer, having a center-tapped primary, may be used. Even higher output powers can be obtained using emitter-followers. In Figure 31, the supply voltage to the AD8306 is dropped from 5 V to about 4.2 V, by the diode. This increases the available swing at each output to about 2 V. Taking both outputs differentially, a square wave output of 4 V p-p can be generated. When operating at high output power levels and high frequencies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is low, due to the extremely high gain-bandwidth product of the AD8306 under such conditions. These oscillations will be less evident when signal-balancing networks are used, operating at frequencies below 200 MHz, and they will generally be fully quenched by the signal at input levels of a few dB above the noise floor.

Modulated Limiter Output
The limiter output stage of the AD8306 also provides an analog multiplication capability: the amplitude of the output square wave can be controlled by the current withdrawn from LMDR (Pin 9). An analog control input of 0 V to +1 V is used to generate an exactly-proportional current of 0 mA to 10 mA in the npn transistor, whose collector is held at a fixed voltage of ∼400 mV by the internal bias in the AD8306. When the input signal is above the limiting threshold, the output will then be a squarewave whose amplitude is proportional to the control bias.

Effect of Waveform Type on Intercept
The AD8306 fundamentally responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power, but differing crest factors, will produce different results at the log amp's output.
The effect of differing signal waveforms is to shift the effective value of the log amp's intercept. Graphically, this looks like a vertical shift in the log amp's transfer function. The device's logarithmic slope however is not affected. For example, consider the case of the AD8306 being alternately fed by an unmodulated sine wave and by a single CDMA channel of the same rms power. The AD8306's output voltage will differ by the equivalent of 3.55 dB (71 mV) over the complete dynamic range of the device (the output for a CDMA input being lower). Table II shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A sine wave input is used as a reference. To measure the rms power of a square wave, for example, the mV equivalent of the dB value given in the table (20 mV/dB times 3.01 dB) should be subtracted from the output voltage of the AD8306.

Evaluation Board
An evaluation board, carefully laid out and tested to demonstrate the specified high speed performance of the AD8306 is available. Figure 33 shows the schematic of the evaluation board, which fairly closely follows the basic connections schematic shown in Figure 27. For ordering information, please refer to the Ordering Guide. Links, switches and component settings for different setups are described in Table III.

SW1
Device Enable. When in Position A, the ENBL pin is connected to +V S and the SW1 = A AD8306 is in normal operating mode. In Position B, the ENBL pin is connected to an SMA connector labeled Ext Enable. A signal can be applied to this connector to enable/disable the AD8306.

R1
This pad is used to ac-couple INLO to ground for single-ended input drive. To drive R1 = 0 Ω the AD8306 differentially, R1 should be removed. R/L, C1, C2 Input Interface. The 52.3 Ω resistor in position R10, along with C1 and C2, create R10 = 52.3 Ω a high-pass input filter whose corner frequency (640 kHz) is equal to 1/(2πRC), C1 = C2 = 0.01 µF where C = (C1)/2 and R is the parallel combination of 52.3 Ω and the AD8306's input impedance of 1000 Ω. Alternatively, the 52.3 Ω resistor can be replaced by an inductor to form an input matching network. See Input Matching Network section for more details.
Resistors) = 50 Ω To disable the limiter (recommended if the limiter is not being used), LK1 should be removed.