Comparator

This application note describes how the NCP3063 can be configured as a buck controller to drive an external PFET transistor to produce a cost effective, high efficiency 3 A switching regulator. The NCP3063 has a wide input voltage range up to 40 V which makes it attractive for industrial and consumer applications such as LCD-TVs. The design example illustrates a buck converter delivering 3 A at 5 or 3.3 V from a 12 V supply. The block diagram of the NCP3063 controller is shown in FigureĂ1. This switching regulator is based on a very flexible " gated oscillator or bust mode " architecture that can be used to create step-down (buck), step-up (boost) and buck-boost voltage regulators. The NCP3063 contains an internal switch capable of up to 1.5 A but in applications requiring higher current, this device can be configured as a controller driving an external MOSFET.

This application note describes how the NCP3063 can be configured as a buck controller to drive an external PFET transistor to produce a cost effective, high efficiency 3 A switching regulator.The NCP3063 has a wide input voltage range up to 40 V which makes it attractive for industrial and consumer applications such as LCD-TVs.The design example illustrates a buck converter delivering 3 A at 5 or 3.3 V from a 12 V supply.
The block diagram of the NCP3063 controller is shown in FigureĂ1.
This switching regulator is based on a very flexible "gated oscillator or bust mode" architecture that can be used to create step-down (buck), step-up (boost) and buck-boost voltage regulators.The NCP3063 contains an internal switch capable of up to 1.5 A but in applications requiring higher current, this device can be configured as a controller driving an external MOSFET.For detailed information regarding controller operation refer to the NCP3063 data sheet.The essentials of the control method can be observed in the waveforms of FigureĂ2.The output voltage is fed back to the inverting input 5 of the comparator (Figure 1) via a resistor divider.If the output is below the set point, the comparator "gates" a series of clock cycles through the power switch.Control of the output voltage is achieved by varying the average number of "on cycles" to the number of "off cycles" in a given time interval.
The transfer function (or gain) V OUT/ V IN for a conventional buck converter, neglecting circuit losses, is given by the following equation: If the value for D MAX (0.86) set by the NCP3063 is inserted into the above equation, the maximum gain is determined.
This maximum gain value may be considerably more than a particular application requires.For example, a typical 12ĂV to 5 V buck application requires a gain of 0.42 and a corresponding D = 0.42.Consequently the "gated oscillator" operates at a small effective duty cycle, delivering power to the load for a few switching cycles before turning off for extended periods.The burst mode frequency is low causing the converter's output ripple to be high.The design may be optimized as follows.
The NCP3063 oscillator section consists of two current sources; one charging, the other discharging the timing capacitor C T , between two fixed voltage levels (Figure 3).The levels are approximately 500 mV apart.The ratio between the charge current and the discharge current is set within the controller to be 1:6.This ratio creates a fixed duty cycle D MAX of 6/7 or 0.86.The ramp circuit is modified (also illustrated in Figure 3) by adding of an external current source I FF to I CHARGE at the C T pin.This current source, in the simplest case, is created by adding a feedforward resistor between V IN and C T .(Additional information is available in the application note AND8284.)Adding an external current will reduce the time it takes to charge the C T capacitor between the ramps's minimum and maximum thresholds.The design equations relating to the oscillator section are given below.
T ON + C T @ DV RAMP Ăń ȍI CHARGE (eq. 3) T OFF + C T @ DV RAMP Ăń ȍI DISCHARGE (eq.4) T S + (T ON ) T OFF ) (eq. 5) D MOD + T ON ĂńĂT S (eq. 6) F S + 1ĂńĂT S (eq.7) Table 1 shows the corresponding reduction in duty cycle D MOD as a normalized function of the charging and discharging currents flowing into the timing capacitor C T .
The table also shows the change in normalized oscillator frequency.Once an optimum duty cycle has been identified and I FF selected, the value of C T can be ratio metrically increased to reset the design frequency.This done, the converter's design frequency remains constant over a wide range of operating conditions.Variation of duty cycle D MOD and frequency F MOD as a function of normalized external current, charging the timing capacitor C T .

Practical Example
Figure 4 is a schematic of the buck converter.The input is a nominal 12 V while the output is regulated to 5 V.The NCP3063 is used as the imbedded controller driving an external PFET switch.

RTN
The selection of the timing capacitor C T (C4) and feedforward resistor R6 is discussed next.
Assuming no circuit losses, the transfer function or gain of this application is 0.42 and is also 0.42.Referring to TableĂ1, a 3:1 ratio for the external charging current to internal charging current would generate a modified duty D MOD of 0.5.This is a good starting point.
The nominal charge and discharge currents for the NCP3063 are listed below: -charging current is 260 mA @ 5 V V CC / 25°C and 280ĂmA @ 40 V V CC / 25°C.
Assume we chose to operate at a switching frequency of approximately 200 kHz.Then T S is 5 mS and T ON is 2.5 mS giving the required modified duty cycle D MOD of 0.5.Rearranging Equation 3, a value for the timing capacitor CT is obtained: Substituting values of ∑I CHARGE of 4 x 260 mA and ΔV RAMP of 0.6 V into Equation 8, gives a nominal value of C T as 4.3 nF.The nearest standard value for C T is 3.9 nF.
The value of R6 is selected as follows.Assume the average amplitude of the ramp waveform is 0.9 V. We require an external charging current I FF of 3 x 260 mA, hence R6 equals (12 V -0.9 V) / 780 mA or 14.2 kW.The nominal value selected for R6 was 15 kW

Selection of External Transistor Q1
Given the design requirements for a 12 V input and 3 A output buck converter running with low ripple current in continuous conduction mode, the maximum switch current and voltage ratings of the MOSFET must be considered.A 20 V, 5 A, 26 mW PFET such as the NTMS5P02 meets our criteria with margin for de-rating.For a smaller package footprint, the NTHS5441T1G PFET could also be an option, depending on output current and thermal considerations.
The R DS(on) and total gate charge Q g curves for ONĂSemiconductor's NTMS5P02R2 P channel MOSFET are shown in Figures 6 and 7.The conduction loss P Q1 is given by Equation 9.
P Q1 +Ă ńĂI OUT ā 2 @ R DS(on) @ D MOD (eq.9) P Q1 = 3 2 * 26 mW * 0.43 = 101 mW A 5.6 V zener diode D2 (Figure 4) is used to drop the gate drive voltage V GS below V IN The gate power P G required to switch the FET channel on and off is given by: (eq. 10) For V GS = 4.5 V, the gate charge Q G (from Figure 6) is 20ĂnC P G = 20 nC * 4.5 V * 200 kHz = 180 mW The gate drive waveform is captured in Figure 8.The network consisting of a small signal NPN transistor Q2, D1 and R2, illustrated in the schematic (Figure 4) provides a fast turn off for the PFET Q1.
The turn on/off behavior of the external PFET Q1 is determined as follows.When the internal switch within the NCP3063 turns "on", the gate charge for Q1 is provided by current flowing from V IN via D1 and D2 to ground return.The positive voltage across D1 creates a reverse bias condition across Q2's base emitter junction.Q2 remains in the off state until the internal switch in the NCP3063 is itself turned "off".At this time, current flowing through resistor R2 is diverted to provide Q2 base current.Q2 conducts until Q1's gate charge is neutralized.The value selected for L 1 determines the AC ripple current in the inductor as well as the output current boundary between discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operation.
The ripple current ΔI L1 flowing in the output inductor I L1 is calculated from the standard flux equation Since CCM was selected to keep the peak current to a minimum, a peak ripple of 20 % of the output current (3 A) is our design criteria, requiring ΔI L1 to be 0.6 A. Also (V IN -V OUT ) = 7 V, D MOD = 0.43 and T S = 5 mS, so L 1 may be determined by substitution into equation 11.The required output inductor value is 25 mH.A 22 mH inductor would meet our design objective and is commercially available from several vendors.For example, part number SLF12575T-220M4R0 is a 22 mH inductor from TDK with a winding resistance R W of 26 mW and rated DC current of 4ĂA.The winding loss P L1 in the output inductor is given by the equation, P L1 + I OUT ā 2 @ R W (eq. 12) By employing the feedforward technique, the maximum flux (VmS) the component "sees" has been reduced.Being able to selecting a lower value for L 1 reduces the winding resistance R W , improving converter efficiency.

Selection of Freewheel Diode D1
Figure 9 shows the forward drop of the MBRD320 series of SWITCHMODEt power rectifiers in a DPAK surface mount package.
As can be seen from Figure 9, the typical forward drop V FWD at 3.0 A is 0.4 V at 75°C.The conduction loss P FWD for the free wheel diode is given by the equation: (eq. 13) P FWD = 3.0 A * 0.4 V * 0.43 = 0.52 W

Selection of Input and Output Capacitors
The input and output voltage peak to peak ripple across C1 and C2 are given by the equations below: (eq. 15) Small value MLCC capacitors in 805 and 1206 SMD packages can be an alternative to electrolytic or tantalum capacitors.These MLCCs have extremely low ESR (2ĂmW) and ESL (100 nH) parasitic values and so individually or in parallel combinations can form the "perfect" lossless capacitor when used for filtering at mid to high switching frequencies.
For example if C1 = C2 = 10 mF, ΔI L1 = 0.6 A and D MOD = 0.43, the peak to peak voltage ripple ΔV C across the input and output of the converter are 130 mV and 171 mV respectively.However as the NCP3063 controls the output voltage by gating the oscillator on and off, additional electrolytic or tantalum capacitances C11 and C12 are required at the input and output to filter these lower frequencies.

Current Limit
The NCP3063 has a peak current limit sense circuit, set by connecting a sense resistor R1 (Figure 4) between pins 7 and 8 of the controller.The reference voltage for the current limit function is nominally 200 mV so selecting a 50 milliohm resistor for R1 allows the converter to operate above 3ĂA before current limit protection is activated.The power loss in the sense resistor is 3 2 * R1 or Ps = 450 mW.

Bias Current
The maximum bias current to power the NCP3063 is 7ĂmA.Bias power P B is 84 mW.

Loss Budget
Summing the theoretical losses for Q1's conduction and gate drive, inductor winding, freewheel diode , current sense and bias power, we obtain a loss budget of 101 mW +180ĂmW + 234 mW + 520 mW + 450 mW + 84 mW or 1.57ĂW, neglecting hysteresis losses in the inductor and esr losses in the input and output capacitors.The converter's maximum theoretical efficiency is 15/16.57or 90.5%.

Experimental Results
The efficiency of the buck converter at 5 V and 3.3 V output is shown in Figure 10.The 5.0 V output data is in good agreement with the calculated loss budget above.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).SCILLC reserves the right to make changes without further notice to any products herein.SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages."Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.SCILLC is an Equal Opportunity/Affirmative Action Employer.This literature is subject to all applicable copyright laws and is not for resale in any manner.

Figure
Figure 1.Block Diagram of the NCP3063

Figure
Figure 2. Typical Operating WaveformsOperation Startup

Figure
Figure 3. Current Sources Charging andDischarging the Timing Capacitor C T

Figure 5 .
Figure 5. Ramp Waveform C T = 3900 pF, T S = 4.88 mS With the values selected the observed ramp was captured in Figure 5.The measured values are given below.T ON = 2.10 mS T S = 4.88 mS F S = 205 kHz ΔV RAMP = 0.54 V ΔV AVG = 0.94 V D MOD = 2.1 / 4.88 = 0.43.The experimental duty cycle is close to our actual design requirement of D MOD = 0.42.

Figure 6 .
Figure 6.R DS(on) vs. Drain Current I D NTMS5P02R2 -I D , DRAIN CURRENT (A)

Figure 8 .
Figure 8. High Side Gate Drive for PFET Q1 with Clock Ramp

Figure
Figure 10.Measured Efficiency Data